1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to an oxidation and etchback process for forming a thick contact area on a polysilicon layer in a semiconductor structure.
2. Description of the Related Art
A microelectronic flash or block erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory are made small by omitting select transistors which would enable the cells to be erased independently. All of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide-Semiconductor (MOS) memory cells, each of which includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block.
A type of flash EEPROM memory to which the present invention is especially applicable has a NAND architecture and is designated by the reference numeral 10 in FIG. 1. A NAND flash EEPROM has certain advantages over more conventional NOR type EEPROMs, in which the memory cells are connected to bitlines in a parallel manner. In a NAND EEPROM, the cell size is reduced by connecting the cells in series between bit lines and source lines, thereby eliminating contacts to the individual cells. A NAND EEPROM typically occupies approximately 85% of the area of a NOR EEPROM. Another advantage of a NAND EEPROM is lack of disturb conditions which result in programming or erasure of unselected cells during programming or erasure of selected cells.
The memory 10 includes a plurality of wordlines W.sub.0 to W.sub.n which are connected to a wordline circuit 12 and are used to select rows of cells in the memory 10. Drain bitlines BD.sub.0 to BD.sub.m which are connected to a drain or V.sub.DD circuit 14 and source bitlines BS.sub.0 to BS.sub.m which are connected to a source or V.sub.SS circuit 16 are used in combination to select columns of cells in the memory 10. A drain select line Sel.sub.D and a source select line Sel.sub.S are also connected to the wordline circuit 12.
A plurality of Metal-Oxide-Semiconductor transistors which constitute select cells and memory cells are connected to the wordlines, bitlines and select lines. More specifically, the drains of drain select transistors TD.sub.0 to TD.sub.m are connected to the drain bitlines BD.sub.0 to BD.sub.m respectively, with the gates of the transistors TD.sub.0 to TD.sub.m all being connected to the drain select line SelD. Similarly, the sources of source select transistors TS.sub.0 to TS.sub.m are connected to the source bitlines BS.sub.0 to BS.sub.m respectively, with the gates of the transistors TS.sub.0 to TS.sub.m all being connected to the source select line SelS.
Memory cell transistors T.sub.0,0 to T.sub.0,n are connected in series between the source of the drain select transistor TD.sub.0 and the drain of the source select transistor TS.sub.0. Control gates of the transistors T.sub.0,0 to T.sub.m,0 are connected to the wordline W.sub.0. Memory cell transistors T.sub.1,0 to T.sub.m,n are similarly connected between the drain bitlines BD.sub.1 to BD.sub.m and source bitlines BD.sub.1 to BD.sub.m and to the wordlines W.sub.1 to W.sub.n to form an array of n x m memory cells. The memory cell transistors differ from the select transistors in that they additionally include a floating gate between their control gates and channels.
The memory cell transistors are typically formed in a p-well of an n-type semiconductor substrate which is not shown. The drain select gates TD.sub.0 to TD.sub.m are provided to ensure cell selectivity, whereas the source select gates TS.sub.0 to TS.sub.m are turned off during programming to prevent current flow through the cells.
The cells are erased by controlling the wordline circuit 12, drain circuit 14 and source circuit 16 to ground the control gates, apply a voltage on the order of +20 v to the n-substrate and p-well, and allow the bitlines to float. Electrons are caused to flow from the floating gates to the p-well by Fowler-Nordheim tunneling. The floating gates attain a positive charge, and the threshold voltages of the erased cells become negative. The erased cells function as depletion mode transistors.
An individual memory cell is programmed to a logical "1" state by applying typically +20 v to its control gate through its wordline and typically +7 v to the wordlines of the unselected cells. The p-well is grounded. The selected drain bitline is grounded and +7 v is applied to the unselected drain bitlines. The unselected transistors in the selected bitline are turned on and act as pass gates for the selected transistor. Electrons are injected from the p-well to the floating gate of the selected transistor by Fowler-Nordheim tunneling to cause the floating gate to attain a negative charge and a positive threshold voltage. The programmed cells function as enhancement mode transistors.
A cell is read by applying 0 v to its control gate and +5 v to the control gates of the unselected transistors in the selected bitline. The unselected transistors are turned on and act as pass gates for the selected transistor. The cell is read by a sense amplifier (not shown) which is connected to the bitlines. If the cell is not programmed (logical "0"), it will be in depletion mode and current will flow therethrough to the sense amplifier because the 0 v on the control gate will not overcome the negative threshold voltage and turn off the transistor. If the cell is programmed (logical "1") , it will be in enhancement mode and current will not flow therethrough to the sense amplifier because the 0 v on the control gate will not overcome the positive threshold voltage and turn on the transistor.
FIG. 2 is a simplified view illustrating the overall arrangement of a first polysilicon layer (POLY 1) the memory 10. The memory 10 includes a semiconductor substrate 18, typically n-doped silicon, in which active core source/drain areas 20a, 20b and 20c which include p-wells are formed. In this simplified view, only three active areas are shown, whereas in the actual memory 10 there will be m active areas corresponding to the m bitlines. The active areas are separated from each other by electrically insulating core field oxide 21.
Floating gates 22a.sub.0 to 22a.sub.3 are formed over channel regions of memory cell transistors in the active area 20a. Floating gates 22b.sub.0 to 22c.sub.4 are similarly formed over channel regions in the active areas 20b and 20c. The drain select line Sel.sub.D and the source select line Sel.sub.S which were described above with reference to FIG. 1 are formed on the substrate 18 and cross the active areas 20a to 20c. The portions of the select lines SEL.sub.D and SEL.sub.S that overlie the active areas constitute the control gates of the corresponding select transistors TD.sub.0 to TD.sub.m and TS.sub.0 to TS.sub.m as described above.
The select lines and floating gates are integrally patterned from the POLY 1 layer. The select lines Sel.sub.D and Sel.sub.S have contact areas 24 and 26 which are used to provide external connection through vertical interconnects (vias) as will be described in detail below.
FIG. 3 illustrates the structure of the select and memory cell transistors. This drawing illustrates a p-well of the substrate 18. A select transistor 30 includes an n-doped drain 32 and an n-doped source 34, with a portion of the p-well therebetween constituting a channel 36. A gate oxide layer 38 is formed over the channel 36, whereas a portion of the drain select line Sel.sub.D constitutes a gate 40 of the transistor 30.
A memory cell transistor 42 is laterally spaced from the select transistor 30, and includes a drain which is integral with the source 34 of the select transistor 30. The transistor 42 has a source 44 which is spaced from the drain 34 by a channel 46. A tunnel oxide layer 48 through which the above described Fowler-Nordheim tunneling occurs is formed over the channel 46.
A floating gate 50 which is part of the POLY 1 layer as described above is formed over the tunnel oxide layer 48. A gate oxide layer 52 is formed over the floating gate 50, whereas a control gate 54 is formed from a second polysilicon layer (POLY 2) over the gate oxide layer 52. The control gate 54 is connected to one of the wordlines although not illustrated in the drawing. A memory cell transistor 56 is connected in series with the transistor 42 in the arrangement described above with reference to FIG. 1. The entire structure is protectively encapsulated by an electrically insulating passivation layer 58 of, preferably, tetraethylorthosilicate (TEOS) glass.
The arrangement of the select line Sel.sub.D (the select line Sel.sub.S is essentially similar) is illustrated in FIG. 4, and includes the select transistor 30 as well as an adjacent select transistor 60. Gate oxide layers 62 and 64 are formed over channels of the select transistors 30 and 60 in the active areas 20a and 20b respectively, whereas portions of the POLY 1 layer SelD which overlie the gate oxide layers 62 and 64 constitute the gates of the transistors 30 and 60.
In order to provide external connection of the select line Sel.sub.D with other elements of the memory 10, a vertical interconnect hole or via 68 is etched down through the TEOS layer 58 to the contact area 24 of the POLY 1 layer. The via 68 is filled with tungsten metal or other electrically conductive material which forms an ohmic contact 70 with the contact area 24. Electrical connection of the select line Sel.sub.D to the wordline circuit 12 is made through the contact 70.
The via 68 is conventionally formed using reactive ion etching (RIE), which is an anisotropic dry etching process that forms clean vertical holes with high aspect ratios. A goal of the etching process is to stop the etching operation right on the top of the POLY 1 layer select line SEL.sub.D. If the etching does not reach the POLY 1 layer, electrical contact to the POLY 1 layer cannot be made. Conversely, if the etching continues into or through the POLY 1 layer, highly undesirable results can occur.
Design rules for microelectronic circuits require that all parameters have a certain scale with relation to each other. Reduction of feature size to produce a smaller microelectronic device requires that all parameters be reduced together. Reduction in horizontal size requires a corresponding reduction in vertical size.
As microelectronic technology advances, the thickness of the POLY 1 layer is being progressively reduced from approximately 900 angstroms to 700 angstroms. Further reductions to the order of 400-500 angstroms are contemplated in the near future. With the POLY 1 layer is being made progressively thinner, it becomes progressively more difficult to stop via etching right on the top of the POLY 1 layer.
FIG. 5 illustrates a case in which etching proceeded longer than desired, and resulted in the via 68 cutting partially through the contact area 24. This results in an undesirable reduction in contact area between the metal in the via 68 and the POLY 1 layer, and thereby higher electrical resistance. FIG. 6 illustrates a case in which the via etching punched through the POLY 1 layer and also through the field oxide layer 21 into the substrate 18. This is a major problem since the contact 70 will be shorted to the substrate 18.
Such a condition can readily result because the field oxide layer 21 is only approximately 2,000 angstroms thick and the etchant which is used for RIE, typically Cl.sub.2 +HBr, etches silicon dioxide approximately 20 times faster than polysilicon. Thus, if the etching punches through the thin polysilicon layer POLY 1, it can quickly punch through the field oxide layer 21 into the substrate 18.